module REGS(busA, busB, busW, RA, RB, RW, RegWr, clk);
    output [31:0] busA, busB;
    input [31:0] busW;
    input [4:0] RA, RB, RW;
    input RegWr, clk;

//    reg [31:0] busA, busB;
    reg [31:0] regs[0:31];

    always @(posedge clk)
        regs[0] = 32'h0;

//    always @ (RA)
  assign    busA = regs[RA];

//    always @ (RB)
  assign    busB = regs[RB];

    always @(posedge clk)
    begin
        if (RegWr == 1'b1 && RW != 5'h0)
            regs[RW] = busW;
    end
endmodule
